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onenand128 flash memory 1 onenand specification version: ver. 1.0 product part no. v cc (core & io) temperature pkg onenand128 kfg2816q1m-deb 1.8v(1.7v~1.95v) extended 67fbga(lf)/48tsop1 kfg2816d1m-deb 2.65v(2.4v~2.9v) extended 67fbga(lf)/48tsop1 kfg2816u1m-dib 3.3v(2.7v~3.6v) industrial 67fbga(lf)/48tsop1 date: june 15th, 2005
onenand128 flash memory 2 information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsung products, contact your nearest samsung office. 2. samsung products are not intended for use in life su pport, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or phy sical harm, or any military or defense application, or any governmental pr ocurement to which special terms or provisions may apply. onenand ? ? is a trademark of samsung electronics company, ltd. other names and brands may be claimed as the property of their rightful owners. copyright ? 2005, samsung electronics company, ltd
onenand128 flash memory 3 document title onenand revision history the attached datasheets are prepared and approved by samsung elec tronics. samsung electronics co., ltd. reserve the right to change the specifications. sams ung electronics will evaluate and reply to y our requests and questions about device. if you h ave any questions, please c ontact the samsung branch office near you. revision no. 0.0 0.1 1.0 remark advance advance draft date sep. 9, 2004 oct. 28, 2004 jun. 15, 2005 history 1. initial issue. 1. corrected the errata 2. revised cold reset 3. added tsop1 package information 4. revised fbga package type 5. added 67fbga package information 6. revised typical totp, tlock from 300us to 600us 7. revised max totp, tlock from 600us to 1000us 8. deleted lock all block, lock-tight all block operation 9. added endurance and data retention 10. revised load data into buffer operation sequence 11. revised warm reset 12. revised programmable burst read latency timing diagram 13. revised multi block erase flow chart 14. revised extended operating temperature 1. added copyright notice in the beginning 2. corrected errata 3. updated icc2, icc4, icc5, icc6 and i sb 4. revised int pin description 5. added otp erase case note 6. revised case definitions of interrupt status register 7. added a note to command register 8. added ecclogsector information table 9. removed ?data unit based data handli ng? from description of device operation 10. revised description on warm/hot/nand flash core reset 11. revised warm reset timing 12. revised description for 4-, 8-, 16-, 32-word linear burst mode 13. revised otp operation description 14. added note for otp l in internal register reset 15. removed all block lock default case after cold or warm reset 16. added explanation for each prohibited case in protect mode 17. revised the case of writing ot her commands during multi block erase routine 18. added note for erase suspend/resume 19. added supplemental expl anation for ecc operation 20. removed classification of ecc error from ecc operation 21. removed redundant sentance from ecc bypass operation 22. added technical note for boot sequence 23. added technical note for int pin connection guide 24. excluded toeh from asynchronous read table 25. revised asycnchronous read timing diagram for ce don?t care mode 26. revised asynchronous write timing diagram for ce don?t care mode 27. revised load operation timing diagram for ce don?t care mode
onenand128 flash memory 4 1. features ? design technology: 0.12 m ? voltage supply - 1.8v device(kfg2816q1m) : 1.7v~1.95v - 2.65v device(kfg2816d1m) : 2.4v~2.9v - 3.3v device(kfg2816u1m) : 2.7v~3.6v ? organization - host interface:16bit ? internal bufferram(3k bytes) - 1kb for bootram, 2kb for dataram ? nand array - page size : (1k+32)bytes - block size : (64k+2k)bytes ? architecture ? host interface type - synchronous burst read : clock frequency: up to 54mhz : linear burst - 4 , 8 , 16 , 32 words with wrap-around : continuous sequential burst(512 words) - asynchronous random read : access time of 76ns - asynchronous random write ? programmable read latency ? multiple sector read - read multiple sectors by sector count register(up to 2 sectors) ? multiple reset - cold reset / warm reset / hot reset / nand flash reset ? power dissipation (typical values, c l =30pf) - standby current : 10ua@1.8v device, 15ua@2.65v/3.3v device - synchronous burst read current(54mhz) : 12ma@1.8v device, 20ma@2.65v/3.3v device - load current : 20ma@1.8v device, 20ma@2.65v/3.3v device - program current: 20ma@1.8v device, 20ma@2.65v/3.3v device - erase current: 15ma@1.8v device, 18ma@2.65v/3.3v device ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years ? performance ? voltage detector generating internal reset signal from vcc ? hardware reset input (rp ) ? data protection - write protection mode for bootram - write protection mode for nand flash array - write protection during power-up - write protection during power-down ? user-controlled one time programmable(otp) area ? internal 2bit edc / 1bit ecc ? internal bootloader supports booting solution in system ? hardware features ? handshaking feature - int pin: indicates ready / busy of onenand - polling method: provides a software method of detecting the ready / busy status of onenand ? detailed chip information by id register ? software features ? package - 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch fbga - 48 tsop 1, 12mm x 20mm, 0.5mm pitch ? packaging
onenand128 flash memory 5 2. general description onenand is a single-die chip with standard nor flash interface using nand flash array. this device is comprised of logic and nand flash array and 3kb internal bufferram. 1kb bootram is used for reserving bootcode, and 2kb dataram is used for buff- ering data. the operating clock frequency is up to 54mhz. this dev ice is x16 interface with ho st, and has the speed of ~76ns ra ndom access time. actually, it is ac cessible with minimum 4clock la tency(host-driven clock for sync hronous read), but this device ad opts the appropriate wait cycles by programmable read latency. onenand provides the multiple sector read operation by assigning the num- ber of sectors to be read in the sector counter register. t he device includes one block sized otp(one time programmable), whic h can be used to increase system security or to provide identification capabilities.
onenand128 flash memory 6 3. pin description note: do not leave power supply(v cc , v ss ) disconnected. pin name type nameand description host interface a15~a0 i address inputs - inputs for addresses during operation, which are for addressing bufferram & register. dq15~dq0 i/o data inputs/outputs - inputs data during program and commands during all operations, outputs data during memory array/ register read cycles. data pins float to high-impedance when t he chip is deselected or outputs are disabled. int o interrupt notifying host when a command has completed. it is open drain output with internal resistor(~50kohms). after power-up, it is at hi-z condition. once iobe is set to 1, it does not float to hi-z condition even when the chip is deselected or when outputs are disabled. rdy o ready indicates data valid in synchronous read modes and is activated while ce is low clk i clock clk synchronizes the device to the syst em bus frequency in synchronous read mode. the first rising edge of clk in conjunction with avd low latches address input. we i write enable we controls writes to the bufferram and registers. datas are latched on the we pulse?s rising edge avd i address valid detect indicates valid address presence on address inputs. during asynchronous read operation, all addresses are latched on avd ?s rising edge, and during synchronous read operation, all addresses are latched on clk?s rising edge while avd is held low for one clock cycle. > low : for asynchronous mode, indicates valid address ;for burst mode, causes starting address to be latched on rising edge on clk > high : device ignores address inputs rp i reset pin when low, rp resets internal operation of onenand. rp status is don?t care during power-up and bootloading. ce i chip enable ce -low activates internal control logic, and ce -high deselects the device, places it in standby state, and places add and dq in hi-z oe i output enable oe -low enables the device?s output data buffers during a read cycle. power supply v cc -core/vcc power for onenand core this is the power supply for onenand core. v cc -io/vccq power for onenand i/o this is the power supply for onenand i/o vcc-io is internally connected to vcc-core, thus should be connected to the same power supply. v ss ground for onenand etc. dnu do not use leave it disconnected. these pins are used for testing. nc no connection lead is not internally connected.
onenand128 flash memory 7 4. pin configuration 4.1 tsop1 (top view, facing down) tsop1 onenand chip 48pin, 12mm x 20mm, 0.5mm pitch tsop1 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c a15 a14 a13 a12 a11 a10 a9 a8 we v ss v cc int avd rp a7 a6 a5 a4 a3 a2 a1 a0 n.c v ss oe dq15 dq7 dq14 dq6 v ss dq13 dq5 dq12 dq4 dq11 dq3 dq10 dq2 v cc q dq9 dq1 dq8 dq0 rdy clk ce v cc 0.5mm pitch
onenand128 flash memory 8 4.2 67fbga nc nc int a0 a1 nc a10 a6 nc nc we rp dq14 v ss v ss dq13 dq12 dq8 dq1 oe dq9 v cc dq7 dq4 dq11 dq10 dq3 v cc dq15 a12 dq0 dq5 dq6 ce dq2 nc nc a9 avd a7 a11 a8 a4 a5 a2 a3 nc core io clk (top view, balls facing down) 67ball fbga onenand chip a15 a13 a14 rdy 67ball, 7.0mm x 9.0mm x max 1.0mmt , 0.8mm ball pitch fbga nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc
onenand128 flash memory 9 terms, abbreviations and definitions b (capital letter) byte, 8bits w (capital letter) word, 16bits b (lower-case letter) bit ecc error correction code calculated ecc ecc which has been calculated during load or program access written ecc ecc which has been stored as data in the nand flash array or in the bufferram bufferram on-chip internal buffer consisting of bootram and dataram bootram a 1kb portion of the bufferram reserved for bootcode buffering dataram a 2kb portion of the bufferram reserved for data buffering memory nand flash array which is embedded on onenand sector partial unit of page, of which size is 512b for main area and 16b for spare area data. it is the minimum load/program/c opy-back program unit while one~two sector operation is available data unit possible data unit to be read from memory to bufferram or to be programmed to memory. - 528b of which 512b is in main area and 16b in spare area - 1056b of which 1024b is in main area and 32b in spare area
onenand128 flash memory 10 5. block diagram bootram host interface clk ce oe we rp avd statemachine bootloader internal registers (address/command/configuration /status registers) error correction logic int - host interface - bufferram(bootram, dataram) - command and status registers - state machine (bootloader is included) - error correction logic - memory(nand flash array, otp) note: 1) at cold reset, bootloader copies boot code(1k byte size) from nand flash array to bootram. dataram bufferram nand flash array otp (one block) rdy figure 1. internal block diagram a15~a0 dq15~dq0
onenand128 flash memory 11 page:1kb+32b sector(main area):512b sector(spare area):16b bootram 0 bootram 1 dataram 0_0 dataram 0_1 bootram sector dataram 0 dataram 1_0 dataram 1_1 dataram 1 { main area data { spare area data (512b) (16b) { main area data { spare area data (512b) (16b) (bufferram) (nand array) figure 2. bufferram and nand array structure block: 64kb+2kb 64pages note : 1) the 1st word of spare area in 1st and 2nd page of every invalid block is reserved for the invalid block information by manufac turer. please refer to page 59 about the details. 2) these words are managed by internal ecc logic. so it is re commended that the important data like lsn(logical sector number) are written. 3) these words are reserved for the future purpose by manuf acturer. these words will be dedicated to internal logic. 4) these words are for free usage. 5) the 5th, 6th and 7th words are dedicated to internal ecc logi c. so these words are only readable. the other words are program- mable by command. 6) eccm 1st, eccm 2nd, eccm 3rd: ecc code for main area data 7) eccs 1st, eccs 2nd: ecc code for 2nd and 3rd word of spare area. { 1 st w eccm 1st eccm 2nd eccm 3rd eccs 1st eccs 2nd lsb msb lsb msb { 2 nd w lsb msb { 3 rd w lsb msb { 4 th w lsb msb { 5 th w lsb msb { 6 th w lsb msb { 7 th w lsb msb { 8 th w lsb msb figure 3. spare area of nand array assignment ffh note1 note1 note2 note2 note2 note3 note3 note3 note4 note4 (note3) main area 256w main area 256w spare area 8w spare area 8w
onenand128 flash memory 12 6. address map for onenand nand array (word order) note 1) the 2nd bit of page and sector address register is don?t care. so the ad dress range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block0 0000h 0000h~00fdh 64kb block32 0020h 0000h~00fdh 64kb block1 0001h 0000h~00fdh 64kb block33 0021h 0000h~00fdh 64kb block2 0002h 0000h~00fdh 64kb block34 0022h 0000h~00fdh 64kb block3 0003h 0000h~00fdh 64kb block35 0023h 0000h~00fdh 64kb block4 0004h 0000h~00fdh 64kb block36 0024h 0000h~00fdh 64kb block5 0005h 0000h~00fdh 64kb block37 0025h 0000h~00fdh 64kb block6 0006h 0000h~00fdh 64kb block38 0026h 0000h~00fdh 64kb block7 0007h 0000h~00fdh 64kb block39 0027h 0000h~00fdh 64kb block8 0008h 0000h~00fdh 64kb block40 0028h 0000h~00fdh 64kb block9 0009h 0000h~00fdh 64kb block41 0029h 0000h~00fdh 64kb block10 000ah 0000h~00fdh 64kb block42 002ah 0000h~00fdh 64kb block11 000bh 0000h~00fdh 64kb block43 002bh 0000h~00fdh 64kb block12 000ch 0000h~00fdh 64kb block44 002ch 0000h~00fdh 64kb block13 000dh 0000h~00fdh 64kb block45 002dh 0000h~00fdh 64kb block14 000eh 0000h~00fdh 64kb block46 002eh 0000h~00fdh 64kb block15 000fh 0000h~00fdh 64kb block47 002fh 0000h~00fdh 64kb block16 0010h 0000h~00fdh 64kb block48 0030h 0000h~00fdh 64kb block17 0011h 0000h~00fdh 64kb block49 0031h 0000h~00fdh 64kb block18 0012h 0000h~00fdh 64kb block50 0032h 0000h~00fdh 64kb block19 0013h 0000h~00fdh 64kb block51 0033h 0000h~00fdh 64kb block20 0014h 0000h~00fdh 64kb block52 0034h 0000h~00fdh 64kb block21 0015h 0000h~00fdh 64kb block53 0035h 0000h~00fdh 64kb block22 0016h 0000h~00fdh 64kb block54 0036h 0000h~00fdh 64kb block23 0017h 0000h~00fdh 64kb block55 0037h 0000h~00fdh 64kb block24 0018h 0000h~00fdh 64kb block56 0038h 0000h~00fdh 64kb block25 0019h 0000h~00fdh 64kb block57 0039h 0000h~00fdh 64kb block26 001ah 0000h~00fdh 64kb block58 003ah 0000h~00fdh 64kb block27 001bh 0000h~00fdh 64kb block59 003bh 0000h~00fdh 64kb block28 001ch 0000h~00fdh 64kb block60 003ch 0000h~00fdh 64kb block29 001dh 0000h~00fdh 64kb block61 003dh 0000h~00fdh 64kb block30 001eh 0000h~00fdh 64kb block62 003eh 0000h~00fdh 64kb block31 001fh 0000h~00fdh 64kb block63 003fh 0000h~00fdh 64kb
onenand128 flash memory 13 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block64 0040h 0000h~00fdh 64kb block96 0060h 0000h~00fdh 64kb block65 0041h 0000h~00fdh 64kb block97 0061h 0000h~00fdh 64kb block66 0042h 0000h~00fdh 64kb block98 0062h 0000h~00fdh 64kb block67 0043h 0000h~00fdh 64kb block99 0063h 0000h~00fdh 64kb block68 0044h 0000h~00fdh 64kb block100 0064h 0000h~00fdh 64kb block69 0045h 0000h~00fdh 64kb block101 0065h 0000h~00fdh 64kb block70 0046h 0000h~00fdh 64kb block102 0066h 0000h~00fdh 64kb block71 0047h 0000h~00fdh 64kb block103 0067h 0000h~00fdh 64kb block72 0048h 0000h~00fdh 64kb block104 0068h 0000h~00fdh 64kb block73 0049h 0000h~00fdh 64kb block105 0069h 0000h~00fdh 64kb block74 004ah 0000h~00fdh 64kb block106 006ah 0000h~00fdh 64kb block75 004bh 0000h~00fdh 64kb block107 006bh 0000h~00fdh 64kb block76 004ch 0000h~00fdh 64kb block108 006ch 0000h~00fdh 64kb block77 004dh 0000h~00fdh 64kb block109 006dh 0000h~00fdh 64kb block78 004eh 0000h~00fdh 64kb block110 006eh 0000h~00fdh 64kb block79 004fh 0000h~00fdh 64kb block111 006fh 0000h~00fdh 64kb block80 0050h 0000h~00fdh 64kb block112 0070h 0000h~00fdh 64kb block81 0051h 0000h~00fdh 64kb block113 0071h 0000h~00fdh 64kb block82 0052h 0000h~00fdh 64kb block114 0072h 0000h~00fdh 64kb block83 0053h 0000h~00fdh 64kb block115 0073h 0000h~00fdh 64kb block84 0054h 0000h~00fdh 64kb block116 0074h 0000h~00fdh 64kb block85 0055h 0000h~00fdh 64kb block117 0075h 0000h~00fdh 64kb block86 0056h 0000h~00fdh 64kb block118 0076h 0000h~00fdh 64kb block87 0057h 0000h~00fdh 64kb block119 0077h 0000h~00fdh 64kb block88 0058h 0000h~00fdh 64kb block120 0078h 0000h~00fdh 64kb block89 0059h 0000h~00fdh 64kb block121 0079h 0000h~00fdh 64kb block90 005ah 0000h~00fdh 64kb block122 007ah 0000h~00fdh 64kb block91 005bh 0000h~00fdh 64kb block123 007bh 0000h~00fdh 64kb block92 005ch 0000h~00fdh 64kb block124 007ch 0000h~00fdh 64kb block93 005dh 0000h~00fdh 64kb block125 007dh 0000h~00fdh 64kb block94 005eh 0000h~00fdh 64kb block126 007eh 0000h~00fdh 64kb block95 005fh 0000h~00fdh 64kb block127 007fh 0000h~00fdh 64kb
onenand128 flash memory 14 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block128 0080h 0000h~00fdh 64kb block160 00a0h 0000h~00fdh 64kb block129 0081h 0000h~00fdh 64kb block161 00a1h 0000h~00fdh 64kb block130 0082h 0000h~00fdh 64kb block162 00a2h 0000h~00fdh 64kb block131 0083h 0000h~00fdh 64kb block163 00a3h 0000h~00fdh 64kb block132 0084h 0000h~00fdh 64kb block164 00a4h 0000h~00fdh 64kb block133 0085h 0000h~00fdh 64kb block165 00a5h 0000h~00fdh 64kb block134 0086h 0000h~00fdh 64kb block166 00a6h 0000h~00fdh 64kb block135 0087h 0000h~00fdh 64kb block167 00a7h 0000h~00fdh 64kb block136 0088h 0000h~00fdh 64kb block168 00a8h 0000h~00fdh 64kb block137 0089h 0000h~00fdh 64kb block169 00a9h 0000h~00fdh 64kb block138 008ah 0000h~00fdh 64kb block170 00aah 0000h~00fdh 64kb block139 008bh 0000h~00fdh 64kb block171 00abh 0000h~00fdh 64kb block140 008ch 0000h~00fdh 64kb block172 00ach 0000h~00fdh 64kb block141 008dh 0000h~00fdh 64kb block173 00adh 0000h~00fdh 64kb block142 008eh 0000h~00fdh 64kb block174 00aeh 0000h~00fdh 64kb block143 008fh 0000h~00fdh 64kb block175 00afh 0000h~00fdh 64kb block144 0090h 0000h~00fdh 64kb block176 00b0h 0000h~00fdh 64kb block145 0091h 0000h~00fdh 64kb block177 00b1h 0000h~00fdh 64kb block146 0092h 0000h~00fdh 64kb block178 00b2h 0000h~00fdh 64kb block147 0093h 0000h~00fdh 64kb block179 00b3h 0000h~00fdh 64kb block148 0094h 0000h~00fdh 64kb block180 00b4h 0000h~00fdh 64kb block149 0095h 0000h~00fdh 64kb block181 00b5h 0000h~00fdh 64kb block150 0096h 0000h~00fdh 64kb block182 00b6h 0000h~00fdh 64kb block151 0097h 0000h~00fdh 64kb block183 00b7h 0000h~00fdh 64kb block152 0098h 0000h~00fdh 64kb block184 00b8h 0000h~00fdh 64kb block153 0099h 0000h~00fdh 64kb block185 00b9h 0000h~00fdh 64kb block154 009ah 0000h~00fdh 64kb block186 00bah 0000h~00fdh 64kb block155 009bh 0000h~00fdh 64kb block187 00bbh 0000h~00fdh 64kb block156 009ch 0000h~00fdh 64kb block188 00bch 0000h~00fdh 64kb block157 009dh 0000h~00fdh 64kb block189 00bdh 0000h~00fdh 64kb block158 009eh 0000h~00fdh 64kb block190 00beh 0000h~00fdh 64kb block159 009fh 0000h~00fdh 64kb block191 00bfh 0000h~00fdh 64kb
onenand128 flash memory 15 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block192 00c0h 0000h~00fdh 64kb block224 00e0h 0000h~00fdh 64kb block193 00c1h 0000h~00fdh 64kb block225 00e1h 0000h~00fdh 64kb block194 00c2h 0000h~00fdh 64kb block226 00e2h 0000h~00fdh 64kb block195 00c3h 0000h~00fdh 64kb block227 00e3h 0000h~00fdh 64kb block196 00c4h 0000h~00fdh 64kb block228 00e4h 0000h~00fdh 64kb block197 00c5h 0000h~00fdh 64kb block229 00e5h 0000h~00fdh 64kb block198 00c6h 0000h~00fdh 64kb block230 00e6h 0000h~00fdh 64kb block199 00c7h 0000h~00fdh 64kb block231 00e7h 0000h~00fdh 64kb block200 00c8h 0000h~00fdh 64kb block232 00e8h 0000h~00fdh 64kb block201 00c9h 0000h~00fdh 64kb block233 00e9h 0000h~00fdh 64kb block202 00cah 0000h~00fdh 64kb block234 00eah 0000h~00fdh 64kb block203 00cbh 0000h~00fdh 64kb block235 00ebh 0000h~00fdh 64kb block204 00cch 0000h~00fdh 64kb block236 00ech 0000h~00fdh 64kb block205 00cdh 0000h~00fdh 64kb block237 00edh 0000h~00fdh 64kb block206 00ceh 0000h~00fdh 64kb block238 00eeh 0000h~00fdh 64kb block207 00cfh 0000h~00fdh 64kb block239 00efh 0000h~00fdh 64kb block208 00d0h 0000h~00fdh 64kb block240 00f0h 0000h~00fdh 64kb block209 00d1h 0000h~00fdh 64kb block241 00f1h 0000h~00fdh 64kb block210 00d2h 0000h~00fdh 64kb block242 00f2h 0000h~00fdh 64kb block211 00d3h 0000h~00fdh 64kb block243 00f3h 0000h~00fdh 64kb block212 00d4h 0000h~00fdh 64kb block244 00f4h 0000h~00fdh 64kb block213 00d5h 0000h~00fdh 64kb block245 00f5h 0000h~00fdh 64kb block214 00d6h 0000h~00fdh 64kb block246 00f6h 0000h~00fdh 64kb block215 00d7h 0000h~00fdh 64kb block247 00f7h 0000h~00fdh 64kb block216 00d8h 0000h~00fdh 64kb block248 00f8h 0000h~00fdh 64kb block217 00d9h 0000h~00fdh 64kb block249 00f9h 0000h~00fdh 64kb block218 00dah 0000h~00fdh 64kb block250 00fah 0000h~00fdh 64kb block219 00dbh 0000h~00fdh 64kb block251 00fbh 0000h~00fdh 64kb block220 00dch 0000h~00fdh 64kb block252 00fch 0000h~00fdh 64kb block221 00ddh 0000h~00fdh 64kb block253 00fdh 0000h~00fdh 64kb block222 00deh 0000h~00fdh 64kb block254 00feh 0000h~00fdh 64kb block223 00dfh 0000h~00fdh 64kb block255 00ffh 0000h~00fdh 64kb
onenand128 flash memory 16 detailed information of address map (word order) -0000h~01ffh: 2(sector) x 512byte(nand main area) = 1kb 0000h~00ffh(512b) bootm 0 (sector 0 of page 0) 0100h~01ffh(512b) bootm 1 (sector 1 of page 0) ? bootram(main area) -0200h~05ffh: 4(sector) x 512byte(nand main area) = 2kb 0200h~02ffh(512b) datam 0_0 (sector 0 of page 0) 0300h~03ffh(512b) datam 0_1 (sector 1 of page 0) 0400h~04ffh(512b) datam 1_0 (sector 0 of page 1) 0500h~05ffh(512b) datam 1_1 (sector 1 of page 1) ? dataram(main area) -8000h~800fh: 2(sector) x 16byte(nand spare area) = 32b 8000h~8007h(16b) boots 0 (sector 0 of page 0) 8008h~800fh(16b) boots 1 (sector 1 of page 0) ? bootram(spare area) -8010h~802fh: 4(sector) x 16byte(nand spare area) = 64b *nand flash array consists of 1k b page size and 64kb block size. 8010h~8017h(16b) datas 0_0 (sector 0 of page 0) 8018h~801fh(16b) datas 0_1 (sector 1 of page 0) 8020h~8027h(16b) datas 1_0 (sector 0 of page 1) 8028h~802fh(16b) datas 1_1 (sector 1 of page 1) ? dataram(spare area)
onenand128 flash memory 17 spare area assignment buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 boots 0 8000h 10000h bi 8001h 10002h managed by internal ecc logic 8002h 10004h reserved for the future use managed by internal ecc logic 8003h 10006h reserved for the current and future use 8004h 10008h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8005h 1000ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8006h 1000ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8007h 1000eh free usage boots 1 8008h 10010h bi 8009h 10012h managed by internal ecc logic 800ah 10014h reserved for the future use managed by internal ecc logic 800bh 10016h reserved for the current and future use 800ch 10018h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 800dh 1001ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 800eh 1001ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 800fh 1001eh free usage datas 0_0 8010h 10020h bi 8011h 10022h managed by internal ecc logic 8012h 10024h reserved for the future use managed by internal ecc logic 8013h 10026h reserved for the current and future use 8014h 10028h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8015h 1002ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8016h 1002ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8017h 1002eh free usage datas 0_1 8018h 10030h bi 8019h 10032h managed by internal ecc logic 801ah 10034h reserved for the future use managed by internal ecc logic 801bh 10036h reserved for the current and future use 801ch 10038h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 801dh 1003ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 801eh 1003ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 801fh 1003eh free usage equivalent to 1word of nand flash
onenand128 flash memory 18 note: - bi: invalid block information >host can use complete spare area exce pt bi and ecc code area. for example, host can write data to spare area buffer except for the area controlled by ecc logic at program operation. >onenand automatically generates ecc code for both main and spare data of memory during program operation in case of ?with ecc? mode , but does not update ecc code to spare bufferram. >when loading/programming spare area, spare area bufferram address( bsa) and bufferram sector count(bsc) is chosen via start bu ffer register as it is. buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 datas 1_0 8020h 10040h bi 8021h 10042h managed by internal ecc logic 8022h 10044h reserved for the future use managed by internal ecc logic 8023h 10046h reserved for the current and future use 8024h 10048h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8025h 1004ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8026h 1004ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8027h 1004eh free usage datas 1_1 8028h 10050h bi 8029h 10052h managed by internal ecc logic 802ah 10054h reserved for the future use managed by internal ecc logic 802bh 10056h reserved for the current and future use 802ch 10058h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 802dh 1005ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 802eh 1005ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 802fh 1005eh free usage equivalent to 1word of nand flash
onenand128 flash memory 19 7. detailed address map for registers address (word order) address (byte order) name host access description f000h 1e000h manufacturer id r manufacturer identification f001h 1e002h device id r device identification f002h 1e004h version id r version identification f003h 1e006h data buffer size r data buffer size f004h 1e008h boot buffer size r boot buffer size f005h 1e00ah amount of buffers r amount of data/boot buffers f006h 1e00ch technology r info about technology f007h~f0ffh 1e00eh~1e1feh re served - reserved for user f100h 1e200h start address 1 r/w nand flash block address f101h 1e202h start address 2 r/w reserved f102h 1e204h start address 3 r/w destination block address for copy back program f103h 1e206h start address 4 r/w destination page & sector address for copy back program f104h 1e208h start address 5 - n/a f105h 1e20ah start address 6 - n/a f106h 1e20ch start address 7 - n/a f107h 1e20eh start address 8 r/w nand flash page & sector address f108h~f1ffh 1e210h~1e3feh reserved - reserved for user f200h 1e400h start buffer r/w number buffer of for the page data transfer to/from the memory and the start buffer address the meaning is with which buffer to start and how many buffers to use for the data transfer f201h~f207h 1e402h~1e40eh reserved - reserved for user f208h~f21fh 1e410h~1e43eh reserved - reserv ed for vendor specific purposes f220h 1e440h command r/w host control and memory operation commands f221h 1e442h system configuration 1 r, r/w memory and host interface configuration f222h 1e444h system configuration 2 -n/a f223h~f22fh 1e446h~1e45eh reserved - reserved for user f230h~f23fh 1e460h~1e47eh reserved - reserv ed for vendor specific purposes f240h 1e480h controller status r controller status and result of memory operation f241h 1e482h interrupt r/w memory command completion interrupt status f242h~f24bh 1e484h~1e496h reserved - reserved for user f24ch 1e498h unlock start block address r/w start memory block address to unlock in write protection mode f24dh 1e49ah unlock end block address r/w end memory block address to unlock in write protection mode f24eh 1e49ch write protection status r current memory write protection status (unlocked/locked/tight-locked) f24fh~feffh 1e49eh~1fdfeh re served - reserved for user
onenand128 flash memory 20 address (word order) address (byte order) name host access description ff00h 1fe00h ecc status register r ecc status of sector ff01h 1fe02h ecc result of main area data r ecc error position of main area data error for first selected sector ff02h 1fe04h ecc result of spare area data r ecc error position of spare area data error for first selected sector ff03h 1fe06h ecc result of main area data r ecc error position of main area data error for second selected sector ff04h 1fe08h ecc result of spare area data r ecc error position of spare area data error for second selected sector ff05h~ffffh 1fe12h~1ff0ah reserved - res erved for vendor specific purposes
onenand128 flash memory 21 7.2 device id register (r): f001h, default=refer to table1 deviceid (device id): device identification, 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 deviceid 7.3 version id register (r): f002h : n/a table 1. device deviceid[15:0] kfg2816q1m 0004h kfg2816d1m 0005h kfg2816u1m 0005h 7.1 manufacturer id register (r): f000h, default=00ech manufid (manufacturer id): manufacturer identificat ion, 00ech for samsung electronics corp. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 manufid 7. address register (word order)
onenand128 flash memory 22 7.4 data buffer size register(r): f003h, default=0400h databufsize : total data buffer size in words in the memory interface used for shrinks equals two buffers of 512 words each(2x512=2 n , n=10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufsize 7.5 boot buffer size register (r): f004h, default=0200h bootbufsize : total boot buffer size in words in the memory interface (512 words=2 9 , n=9) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bootbufsize 7.6 amount of buffers register (r): f005h, default=0201h databufamount : the amount of data buffer=2 (2 n , n=1) bootbufamount : the amount of boot buffer=1 (2 n , n=0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufamount bootbufamount 7.7 technology register (r): f006h, default=0000h tech : technology information, what te chnology is used for the memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te c h tech technology 0000h nand slc 0001h nand mlc 0002h-ffffh reserved
onenand128 flash memory 23 7.8 start address1 register (r/w): f100h, default=0000h fba (nand flash block address): nand flash block address which will be read or programmed or erased. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) fba 7.9 start address2 register (r/w): f101h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000000000) 7.10 start address3 register (r/w): f102h, default=0000h fcba (nand flash copy back block address): nand flash des tination block address which will be copy back programmed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) fcba 7.11 start address4 register (r/w): f103h, default=0000h fcpa (nand flash copy back page address): nand flash destination page address in a block for copy back program operation. fcpa(default value) = 000000 fcpa range : 000000~111111, 6bits for 64 pages fcsa (nand flash copy back sector address): nand flash destination sector address in a page for copy back program operation. fcsa(default value) = 0 fcsa range : 0~1, 1bits for 2 sectors 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) fcpa reserved fcsa device number of block fba 128mb 256 fba[7:0] device number of block fba 128mb 256 fba[7:0]
onenand128 flash memory 24 7.12 start address5 register: f104h : n/a 7.13 start address6 register: f105h : n/a 7.14 start address7 register: f106h : n/a 7.15 start address8 register (r/w): f107h, default=0000h fpa (nand flash page address): nand flash start page address in a bl ock for page read or copy back program or program operation. fpa(default value)=000000 fpa range: 000000~111111 , 6bits for 64 pages fsa (flash sector address): nand flash start sector address in a page for read or copy back program or program operation. fsa(default value) = 0 fsa range : 0~1, 1bits for 2 sectors 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved (00000000) fpa reserved fsa 7.16 start buffer register (r/w): f200h, default=0000h bsc (bufferram sector count): this field specifies the number of sectors to be read or programmed or copy back programmed. its maximum count is 2 sectors at 0(default value)value. for a single sector access, it should be programmed as valu e 1 and it should be programmed as value 0 for two sectors. however internal ram buffer reached to 1 value(max. value), it counts up to 0 value to satisfy bsc value. for example) if bsa=1101, bsc=0, then selected bufferram are ?1101->1100?. bsa (bufferram sector address): it is the place where data is pl aced and specifies the sector 0~1 in the internal bootram and data ram. bsa[ 3 ] is the selection bit between bootram and dataram. bsa[ 2 ] is the selection bit between dataram0 and dataram1. bsa[0] is the selection bit between sector0 and sector1 in the internal bootram and dataram. while one of bootram or dataram0 interfaces with memory, the other ram is inaccessible. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) bsa reserved(0000000) bsc bootram 0 bootram 1 dataram 0_0 dataram 0_1 bootram sector: (512 + 16)byte dataram0 dataram 1_0 dataram 1_1 dataram1 0000 0001 1000 1001 1100 1101 bsc number of sectors 1 1 sector 0 2 sectors { main area data { spare area data bsa
onenand128 flash memory 25 7.17 command register (r/w): f220h, default=0000h command : operation of the memory interface 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command note : 1)?reset onenand?(=hot reset) command makes t he registers(except rdypol , intpol, io be, and otp l bits) and nand flash core into default state as the warm reset(=reset by rp pin). this r/w register describes the operation of the onenand interface. note that all commands should be issued right after int is turned from ready state to busy state. (i.e. right after 0 is writte n to int register.) after any command is issued and the corresponding operation is completed, int goes back to ready state. (00f0h and 00f3h may be accepted during busy state of some operations. refer to the rightmost column of the command register table above.) cmd operation acceptable command during busy 0000h load single/multiple sector data unit into buffer 00f0h, 00f3h 0013h load single/multiple spare sector into buffer 00f0h, 00f3h 0080h program single/multiple sector data unit from buffer 00f0h, 00f3h 001ah program single/multiple spare area sector from buffer 00f0h, 00f3h 001bh copy back program 00f0h, 00f3h 0023h unlock nand array block(s) from st art block address to end block address - 002ah lock nand array block(s) from start block address to end block address - 002ch lock-tight nand array block(s) from start block address to end block address - 0071h erase verify read 00f0h, 00f3h 0094h block erase 00f0h, 00f3h 0095h multi-block erase 00f0h, 00f3h 00b0h erase suspend 00f3h 0030h erase resume 00f0h, 00f3h 00f0h reset nand flash core - 00f3h reset onenand 1) - 0065h otp access 00f0h, 00f3h
onenand128 flash memory 26 7.18 system configuration 1 register (r, r/w): f221h, default=40c0h rm (read mode): this field specifies the selection between asynchronous read mode and synchronous read mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r r rm brl bl ecc rdy pol int pol iob e reserved(0000) bw ps rm read mode 0 asynchronous read(default) 1 synchronous read brl latency cycles 000 8(n/a) 001 9(n/a) 010 10(n/a) 011 3(up to 40mhz) 100 4(default, min.) 101 5 110 6 111 7 brl (burst read latency): this field specifies the initial access latency in the burst read transfer. bl burst length(main) burst length(spare) 000 continuous(default) 001 4 words 010 8 words 011 16 words 100 32 words n/a 101~111 reserved bl (burst length): this field specifies the size of burst length during sync. burst read. wrap around and linear burst. ecc : error correction operation, 0=with correction(default), 1=without correction(by-passed) rdypol : rdy signal polarity 0=low for ready, 1=high for ready((default) intpol : int pin polarity 0=low for interrupt pending , 1=high for interrupt pending (default) iobe : i/o buffer enable for int and rdy signals, int and rdy outputs are highz at power-up, bit 7 and 6 become valid after iobe is set to1. iobe can be reset only by cold reset or by writing 0 to bit 5 of system configuration 1 register. 0=disable(default), 1=enable bwps : boot buffer write protect status, 0=locked(fixed) intpol int bit of interrupt status register int pin output 00 1 10 0
onenand128 flash memory 27 7.22 controller status register (r): f240h, default=0000h ongo : this bit shows the overall internal status of onenand 0=ready, 1=busy lock : this bit shows whether host loads data from nand flash array into locked bootram or programs/erases locked block of nand flas h array. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ongo lock load prog erase error sus prp rstb otp l reserved(000000) to (0) lock locked/unlocked check result 0 unlocked 1 locked error current sector/page load/program/copyback. program/erase result and invalid command input 0pass 1fail error (current sector/page write result): this bit shows current sector/page load/program/copy back program/erase result of flash me mory or whether host puts invalid command into the device. 7.19 system configuration 2 register : f222h : n/a sus erase suspend status 0 erase resume(default) 1 erase suspend sus (erase suspend/resume):this bit shows the erase suspend status. otp l otp locked/unlocked status 0 otp block unlock status(default) 1 otp block lock status(disable otp program/erase) otp l (otp lock status):this bit shows ot p block is locked or unlocked. otp l bit is automatically updated at power-on. to (time out): time out for read/program/copy back program/erase 0=no time out(fixed) load : this bit shows the load operation status 0=ready(default), 1=busy or error case, refer to the table 3 prog (program busy) : this bit shows the program operation status 0=ready(default), 1=busy or error case, refer to the table 3 erase (erase busy) : this bit shows the erase operation status 0=ready(default), 1=busy or error case, refer to the table 3 rstb (reset busy) : this bit shows the reset operation status 0=ready(default), 1=busy or error case, refer to the table 3
onenand128 flash memory 28 table 3. controller status register output for modes. note : 1. erm and/or ers bits in ecc status register at load fail case is 10. (2bits error - uncorrectable) 2. erm and ers bits in ecc status register at load reset case are 00. (no error) 3. multi block erase status should be checked by erase verify read operation. 4. otp erase does not update the regi ster and the previous value is kept. mode controller status register [15:0] ongo lock load prog erase error sus reserved(0) rstb otp l reserved(0) to load ongoing 1 0 1 0 0 0 0 0 0 0/1 00000 0 program ongoing 1 0 0 1 0 0 0 0 0 0/1 00000 0 erase ongoing 1 0 0 0 1 0 0 0 0 0/1 00000 0 reset ongoing 1 0 0 0 0 0 0 0 1 0/1 00000 0 multi-block erase ongoing 1 0 0 0 1 0 0 0 0 0/1 00000 0 erase verify read ongoing 1 0 0 0 0 0 0 0 0 0/1 00000 0 load ok 0 0 0 0 0 0 0 0 0 0/1 00000 0 program ok 0 0 0 0 0 0 0 0 0 0/1 00000 0 erase ok 0 0 0 0 0 0 0 0 0 0/1 00000 0 erase verify read ok 3) 0 0 0 0 0 0 0 0 0 0/1 00000 0 load fail 1) 0 0 1 0 0 1 0 0 0 0/1 00000 0 program fail 0 0 0 1 0 1 0 0 0 0/1 00000 0 erase fail 0 0 0 0 1 1 0 0 0 0/1 00000 0 erase verify read fail 3) 0 0 0 0 1 1 0 0 0 0/1 00000 0 load reset 2) 0 0 1 0 0 1 0 0 1 0/1 00000 0 program reset 0 0 0 1 0 1 0 0 1 0/1 00000 0 erase reset 0 0 0 0 1 1 0 0 1 0/1 00000 0 erase suspend 0 0 0 0 1 0 1 0 0 0/1 00000 0 program lock 0 1 0 1 0 1 0 0 0 0/1 00000 0 erase lock 0 1 0 0 1 1 0 0 0 0/1 00000 0 load lock(buffer lock) 0 1 1 0 0 1 0 0 0 0/1 00000 0 otp program fail(lock) 0 1 0 1 0 1 0 0 0 1 00000 0 otp program fail 0 0 0 1 0 1 0 0 0 0 00000 0 otp erase fail 0 1 0 0 1 1 0 0 0 0/1 00000 0 program ongo- ing(susp.) 1 0 0 1 1 0 1 0 0 0/1 00000 0 load ongoing(susp.) 1 0 1 0 1 0 1 0 0 0/1 00000 0 program fail(susp.) 0 0 0 1 1 1 1 0 0 0/1 00000 0 load fail(susp.) 0 0 1 0 1 1 1 0 0 0/1 00000 0 invalid command 0 0 0 0 0 1 0 0 0 0/1 00000 0 invalid com- mand(susp.) 0 0 0 0 1 1 1 0 0 0/1 00000 0
onenand128 flash memory 29 7.23 interrupt status register (r/w): f241h, default=8080h(after cold reset),8010h(after warm/hot reset) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 int reserved(0000000) ri wi ei rsti reserved(0000) 7.24 start block address (r/w): f24ch, default=0000h sba (lock/unlock/lock-tight start block address): start nand flash block address in write protection mode, which follows ?lock bl ock command? or ?unlock block command? or ?lock-tight command?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) sba 7.25 end block address (r/w): f24dh, default=0000h eba (lock/unlock/lock-tight end block address): end nand flash blo ck address in write protection mode, which follows ?lock block co mmand? or ?unlock block command? or ?lock-tight command?. eba should be equal to or larger than sba. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) eba device number of block sba/eba 128mb 256 [7:0] bit address bit name default state valid states function cold warm/hot 15 int(interrupt): the master interrupt bit 1 1 0 interrupt off - set to ?1? of itself when one or more of ri, wi, ei and rsti is set to ?1?, or unlock(0023h), lock(002ah), lock- tight(002ch), or erase verify read(0071h), or otp access(0065h) operation, or "load data into buffer" is completed. - cleared to ?0? when by writing ?0? to this bit or by reset(cold/warm/hot reset). ?0? in this bit means that int pin is low status. (this int bit is directly wired to the int pin on the chip. int pin goes low upon writing ?0? to this bit when intpol is high and goes high upon writing ?0? to this bit when intpol is low. ) 0->1 interrupt pending 7 ri(read interrupt): 1 0 0 interrupt off - set to ?1? of itself at the completion of load operation (0000h, 0013h, or boot is done.) - cleared to ?0? when by writing ?0? to this bit or by reset (cold/warm/hot reset). 0->1 interrupt pending 6 wi(write interrupt): 0 0 0 interrupt off - set to ?1? of itself at the completion of program operation (0080h, 001ah, or 001bh) - cleared to ?0? when by writing ?0? to this bit or by reset (cold/warm/hot reset). 0->1 interrupt pending 5 ei(erase interrupt): 0 0 0 interrupt off - set to ?1? of itself at the completion of erase operation (0094h, 0095h, or 0030h) - cleared to ?0? when by writing ?0? to this bit or by reset (cold/warm/hot reset). 0->1 interrupt pending 4 rsti(reset interrupt): 0 1 0 interrupt off - set to ?1? of itself at the completion of reset operation (00b0h, 00f0h, 00f3h, or warm reset is released.) - cleared to ?0? when by writing ?0? to this bit. 0->1 interrupt pending
onenand128 flash memory 30 7.27 ecc status register(r): ff00h, default=0000h erm (ecc error for main area data) & ers (ecc error for spare area data) : erm0/1 is for first/second selected sector in main of bufferram, ers0/1 is for first/second selected sector in spare of bufferram. erm and ers show the number of error nits in a sector as a result of ecc check at the load operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) erm1 ers1 erm0 ers0 note : 1. 3bits or more error detection is not supported. erm, ers ecc status 00 no error 01 1-bit error(correctable) 10 2-bit error(uncorrectable) 1) 11 reserved 7.28 ecc result of first selected sector main area data register (r): ff01h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword0 eccposio0 7.29 ecc result of first selected sector spare area data register (r): ff02h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector0 eccposio0 7.30 ecc result of second selected sector main area data register (r): ff03h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword1 eccposio1 7.31 ecc result of second selected sector spare area data register (r): ff04h, default=0000h note : 1. eccposword: ecc error position address that selects one of main area data(256words) 2. eccposio: ecc error position address which selects one of sixteen dqs (dq 0~dq 15). 3. ecclogsector: ecc error position address that selects one of the 2nd word and lsb of the 3rd word of spare area. refer to th e below table. ecclogsector information [5:4] 4. eccposword, eccposio and ecclogsector are updated in boot loading operation, too. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector1 eccposio1 ecclogsector error position 00 2nd word 01 3rd word 10, 11 reserved 7.26 nand flash write protection status (r): f24eh, default=0002h us (unlocked status): ?1? value of this bit specifies that th e current block in nand flash is unlocked. ls (locked status): ?1? value of this bit specifi es that the current block in nand flash is in locked status. lts (lock-tighten status): ?1? value of this bit specifies that current block in nand flash is lock-tighten. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000000) us ls lts
onenand128 flash memory 31 8. device operation the device supports both a limited command based and a register based interface for performing operations on the device, readin g device id, writing data to buffer etc. the command based interfac e is active in the boot partition, i.e. commands can only be written with a boot area address. boot area data is only re turned if no command has been issued prior to the read. 8.1 command based operation the entire address range, except for the boot area, can be used for the data buffer. all commands are written to the boot part ition. writes outside the boot partition are treated as normal writes to the buffers or regi sters. the command consists of one or more cycles depending on the command. after completion of the command the device starts its execution. writing incorrect information which include address and data or writ ing an improper command will terminate the previous command sequence and make the device go to the ready status. the defined valid command sequences ar e stated in table4. table 4. command sequences note: 1) dp(data partition) : dataram area 2) bp(boot partition) : bootram area [0000h ~ 01ffh, 8000h ~ 800fh]. 3) load data into buffer operation is available within a block(64kb) 4) load 1kb unit into dataram0. current start address(fpa) is automatically incremented by 1kb unit after the load. 5) 0000h -> data is manufacturer id 0001h -> data is device id 0002h -> current block write protection status 6) we toggling can terminate ?read identification data? operation. 8.1.1 read data from buffer buffer can be read by addressing a read to a wanted buffer area 8.1.2 write data to buffer buffer can be written by addressing a write to a wanted buffer area 8.1.3 reset onenand reset command is given by writing 00f0h to the boot partition address. reset will return all default values into the devic e. 8.1.4 load data into buffer load data into buffer command is a two-cycle command. two sequential designated command activates this operation. sequential ly writing 00e0h and 0000h to the boot partition [0000h~01ffh, 8000h~800fh] will load one page to dataram0. this operation refers to fba and fpa . fsa, bsa, and bsc are not considered. at the end of this operation, fpa will be automatically in creased by 1. so continuous issue of this command will sequentiall y load data in next page to dataram0. this page address increment is restricted within a block. the default value of fba and fpa is 0. therefore, initial i ssue of this command after power on will load the first page of m emory, which is usually boot code. 8.1.5 read identification data read identification data command consists of two cycles. it gives out the devices identification data according to the given address. the first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in table5. command definition cycles 1st cycle 2nd cycle read data from buffer add 1 dp 1) data data write data to buffer add 1 dp data data reset onenand add 1 bp 2) data 00f0h load data into buffer 3) add 2 bp bp data 00e0h 0000h 4) read identification data 6) add 2 bp xxxxh 5) data 0090h data
onenand128 flash memory 32 table 5. identification data description address data out 0000h manufacturer id 00ech 0001h device id refer to table 1 0002h current block write protection status refer to nand flash write protection status register 8.2 device bus operations note : l=v il (low), h=v ih (high), x=don?t care. operation ce oe we add0~15 dq0~15 rp clk avd standby h x x x high-z h x x warm reset xxxxhigh-zlxx asynchronous write l h l add. in data in h l asynchronous read l l h add. in data out h l load initial burst address l h h add. in x h burst read l l h x burst data out h terminate burst read cycle hxhxhigh-zhxx terminate burst read cycle via rp xxxxhigh-zlxx terminate current burst read cycle and start new burst read cycle h h add in high-z h x
onenand128 flash memory 33 figure 5. cold reset timings note: 1) bootcode copy operation starts 400us later than por activation. the system power should reach 1.7v after por triggering level(typ. 1.5v) within 400us for valid boot code data. 2) 1k bytes bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of nand flash array to bootram. host can read bootcode in bootram(1k bytes) after bootcode copy completion. 3) int register goes ?low? to ?high? on the condition of ?bootcode-copy done? and rp rising edge. if rp goes ?low? to ?high? before ?bootcode-copy done?, int register goes to ?low? to ?high? as soon as ?bootcode-copy done? 8.3 reset mode cold reset at system power-up, the voltage detector in the device detects the rising edge of vcc and releases internal power-up reset sign al which triggers bootcode loading. bootcode loading means that the boot loader in the de vice copies designated sized data(1kb) fr om the beginning of memory to the bootram. system power sleep bootcode copy idle bootcode - copy done por triggering level 3) 2) rp int onenand operation 0 (default) 1 iobe bit 1 (default) intpol bit high-z 1) int bit 0 (default) 1
onenand128 flash memory 34 warm reset warm reset means that the host resets the device by rp pin, and then the device stops all logi c current operation and executes inter- nal reset operation(note 1) synchronized with the falling edge of rp and resets current nand flash core operation synchronized with the rising edge of rp . the device logic will not be reset in case rp pulses shorter than 200ns, but t he device guarantees the logic reset operation in case rp pulse is longer than 200ns. nand flash core reset wi ll abort current nand flash core operation. the contents of memory cells being altered are no longer valid as the data will be partially programmed or erased. warm reset has n o effect on contents of bootram and dataram. figure 6. warm reset timings rp operation or idle internal reset operation nand flash core reset initiated by rp high int muxonenand operation initiated by rp low ce , oe rdy idle high-z high-z high-z operation or idle operation
onenand128 flash memory 35 hot reset hot reset means that the host resets the device by reset comm and(note 2), and then the device logic stops all current operation and executes internal reset operation(note 1) , and resets current na nd flash core operation. hot reset has no effect on contents of bootram and dataram. figure 7. hot reset timings note: 1. internal reset operation means that the device initializes in ternal registers and makes output signals go to default status and bufferram data are kept unchanged after warm/hot reset operations. 2. reset command : command based reset or register based reset 3. bp(boot partition) : bootram area[0000h~01ffh, 8000h~800fh] avd bp(note 3) int a0~a15 we ce or f220h rdy operation or idle onenand reset idle onenand operation high-z dq0~dq15 00f0h or 00f3h
onenand128 flash memory 36 nand flash core reset host can reset nand flash core operati on by nand flash core reset command. nand flash core reset will abort the current nand flash core operation. during a nand flash core reset, the content of memory cellls being altered is no longer valid as the data will be partially programmed or erased. nand flash core reset has an effect on neither contents of bootram and dataram nor register values. figure 8. nand flash core reset timings avd int we ce f220h rdy operation or idle nand flash core reset idle onenand operation high-z 00f0h a0~a15 dq0~dq15
onenand128 flash memory 37 table 6. internal register reset note: 1) rdypol, intpol, and iobe are reset by cold reset. the other bits are reset by cold/warm/hot reset. otp l is not reset but updated by cold reset. 2) ecc status register & ecc result registers are reset when any command is issued. 3) refer to table 1 internal registers default cold reset warm reset (rp ) hot reset (00f3h) hot reset (bp-f0) nand flash reset(00f0h) f000h manufacturer id register (r) 00ech n/a n/a n/a n/a f001h device id register (r) note3 n/a n/a n/a n/a f002h version id register (rr) - n/a n/a n/a n/a f003h data buffer size register (r) 0400h n/a n/a n/a n/a f004h boot buffer size register (r) 0200h n/a n/a n/a n/a f005h amount of buffers register (r) 0201h n/a n/a n/a n/a f006h technology register (r) 0000h n/a n/a n/a n/a f100h start address1 register (r/w): fba 0000h 0000h 0000h 0000h n/a f101h start address2 register (r/w): reserved 0000h 0000h 0000h 0000h n/a f102h start address3 register (r/w): fcba 0000h 0000h 0000h 0000h n/a f103h start address4 register (r/w): fcpa, fcsa 0000h 0000h 0000h 0000h n/a f107h start address8 register (r/w): fpa, fsa 0000h 0000h 0000h 0000h n/a f200h start buffer register (r/w): bsa, bsc 0000h 0000h 0000h 0000h n/a f220h command register (r/w) 0000h 0000h 0000h 0000h n/a f221h system configuration 1 register (r/w) 40c0h 40c0h o (note1) o (note1) n/a f240h controller status register (r) 0000h 0000h 0000h 0000h n/a f241h interrupt status register (r/w) - 8080h 8010h 8010h n/a f24ch lock/unlock start block address (r/w) 0000h 0000h 0000h n/a n/a f24dh lock/unlock end block address (r/w) 0000h 0000h 0000h n/a n/a f24eh nand flash write protection status (r) 0002h 0002h 0002h n/a n/a ff00h ecc status register (r) (note2) 0000h 0000h 0000h 0000h n/a ff01h ecc result of sector 0 main area data register(r) 0000h 0000h 0000h 0000h n/a ff02h ecc result of sector 0 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff03h ecc result of sector 1 main area data register(r) 0000h 0000h 0000h 0000h n/a ff04h ecc result of sector 1 spare area data register (r) 0000h 0000h 0000h 0000h n/a
onenand128 flash memory 38 write protection write protection for bootram at system power-up, the voltage detector in the device detects the rising edge of vcc and releases the internal power-up reset signal which triggers bootcode loading. and the desi gnated size data(1kb) is copied from the beginning of the memory to the bootram. after the bootcode loading is completed, the bootram is always lo cked to protect the significant boot code from accidental writ e. write protection for nand flash array write protection modes the device offers both hardware and software write protection feat ures for nand flash array. the software write protection feat ure is used by writing lock command or lock-tight command to co mmand register; the 002ah or 002ch command is written into f220h register. the partial write protection feature is also permitt ed by writing partial lock(002ah) and partial lock-tight(002ch) c ommand with the start address and the end address to f24ch and f24dh regi sters. the hardware write protection feature is used by execu ting cold or warm reset. the default state is locked, and all nand flash array goes to locked state after cold or warm reset. write protection commands individual or consecutive instant secured block protects code and data by allowing an y block to be locked or lock-tighten. the write protection scheme offers two levels of prot ection. the first allows software-only control of write protection(useful for freque ntly changed data blocks), while the second requires hardware inte raction before locking can be changed(protects infrequently change d code blocks). the following summarize the locking functionality. > all blocks power-up in a locked state. unlock command can unlock these blocks with the start and end block address. > partial lock-tight command makes the part of locked block(s) to be lock-tightened by writing the start and end block address. and lock-tightened state can be returned to lock state only when cold or warm reset is asserted. > only one individual area can be lock-tight ened by partial lock-tight command; i.e lo ck-tightening multi area is not available . > lock-tightened blocks offer the user an additi onal level of write protection beyond t hat of a regular locked block. lock-tigh tened block can?t have it?s state changed by software, it can be changed by warm reset or cold reset. > unlock start or end block address is re flected immediately to the device only when unlock command is issued, and nand flash write protection status register is also updated at that time. > unlocked blocks can be programmed or erased. > only one area can be released from lock state to unlock stat e with unlock command and addresses. this unlocked area can be changed with new unlock command; when new unlock command is issued, last unlocked area is locked again and new area is unlocked. > partial lock command makes the part of unlocked bloc k(s) to be locked with the start and end block address. > only one area can be locked with partial lock command and addres s. this locked area can be changed with new partial lock com- mand; when new partial lock command is issued, last unlocked area is locked again and new area is unlocked. write protection status the block current write protection status can be read in nand fl ash write protection status register(f24eh). there are three bi ts - us, ls, lts -, which are not cleared by hot reset. these write protection status registers are updated when write protection co m- mand is entered. the followings summarize locking status. example) in default, [2:0] values are 010. -> if host executes unlock block operation, then [2:0] values turn to 100. -> if host executes lock-tight bl ock operation, then [2:0] values turn to 001.
onenand128 flash memory 39 figure 9. operations of nand flash write protection unlocked locked > command sequence : start block address+end block address+unlock block command (0023h) > unlocked block can be programmed or erased > an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate software command > only one sequential area can be released to unlock state from lock state ; unlocking multi individual area is not available lock-tighten > command sequence : > lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. a block that is lock-tighten cannot have its state change by software, only by cold or warm reset. > only locked blocks can be lock-tighten by lock-tight command. > lock-tighten blocks revert to the locked state at cold or warm reset : start block address+end block address+lock-tight block command (002ch) > lock-tighten area does not change with any command; when new unlock command is issued including the lock-tighten area, new unlocked command is ignored. > command sequence : > all blocks default to be locked after cold reset or warm reset > unlocked blocks can be locked by using the lock block command and a lock block?s status can be changed to unlock or lock-tight using the appropriate software commands start block address+end block address+lock block command (002ah)
onenand128 flash memory 40 power on figure 10. state diagram of nand flash write protection sba, eba +unlock unlock lock lock lock command lock-tight sba, eba +partial lock-tight command unlock lock sba, eba +partial lock-tight command lock sba, eba +partial lock command lock-tight lock unlock lock-tight lock note ; the below cases are prohibited in write protection modes. case1. unlock sba eba lock-tight unlock case2. lock sba eba lock unlock case3. lock-tight sba eba even though these cases happen, error bit of cont roller status register(f240h)is not updated. sba, eba +partial lock-tight command lock lock lock-tight sustained unlock lock sba, eba +unlock command unlock lock sba, eba +partial lock command with last changed with new sba, eba sba, eba changed with new sba, eba if this case happens, the command is ignored and last status is sustained. if this case happens, the command is ignored and last status is sustained. if this case happens, the selected area changes to be lock-tight.
onenand128 flash memory 41 load operation the load operation is initiated by setting up the start address fr om which the data is to be loaded. the load command is issued in order to initiate the load. the device transfers the data from nand flash array into the bufferram. the ecc is checked and any detected and corrected error is reported in the status response as well as any unrecoverable error. when the bufferram has bee n filled an interrupt is issued to the host in order to read the cont ents of the bufferram. the read from the bufferram consist o f asyn- chronous read mode or synchronous read mode. the status inform ation related to the bufferram fill operation can be checked by the host if required. the device provides dual data buffer memory architecture. the device is capable of data-read operation from one data buffer and data-load operation to the other data buffer simultaneously. refer to the information for more details in "read while load oper ation". figure 11. load operation flow-chart start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes status register host reads data from dataram read completed map out write 0 to interrupt register add: f241h dq=0000h
onenand128 flash memory 42 read operation the device has two read configurations ; asynchronous read and synchronous burst read. the initial state machine makes the device to be automatically entered into asynchron ous read mode to prevent the memory conten t from spurious altering upon device power up or after a hardware reset. no commands are required to retrieve data in asynchronou s mode. the synchronous mode will be enabled by setting rm bit of system configurati on1 register to synchronous read mode. asynchronous read mode (rm = 0) for the asynchronous read mode a valid address s hould be asserted on a0-a15, while driving avd and ce to v il . we should remain at v ih . the data will appear on dq15-dq0. address access time (t aa ) is equal to the delay from valid addresses to valid out- put data. the chip enable access time(t ce ) is the delay from the falling edge of ce to valid data at the outputs. the output enable access time(t oe ) is the delay from the falling edge of oe to valid data at the output. synchronous (burst) read mode (rm = 1) the device is capable of continuous linear burst operation and li near burst operation of a preset length. for the burst mode, t he initial word(t iaa ) is output asynchronously regardless of brl bit in system c onfiguration 1 register. but the host should determine brl bit of system configuration 1 register for the subsequent words of ea ch burst access. the registers also can be read during burst r ead mode by using avd signal with a address. to initiate the synchronous read again, a new address during ce and avd low toggle is needed after the host has completed status reads or the device has completed the program or erase operation. continuous linear burst read the initial word(t iaa ) is output asynchronously regardless of brl bit in system configuration 1 register. subsequent words are output t ba after the rising edge of each successive clock cycle, which automatica lly increments the internal address counter. the rdy out put indicates this condition to th e system by pulsing low. the device will continue to output sequential burst data, wrapping aroun d after it reaches the designated location(see figure 12 for addres s map information) until the system asserts ce high, rp low or avd low in conjunction with a new address. the cold/warm/hot reset or asserting ce high or we low pulse terminate the burst read operation. if the device is accessed synchronous ly while it is set to asynchronous read m ode, it is possible to read out the first data wi thout prob- lems. division add.map(word order) bootm(0.5kw) 0000h~01ffh buffer0 bufm 0(0.5kw) 0200h~03ffh bufm 1(0.5kw) 0400h~05ffh buffer1 reserved main 0600h~7fffh n/a reg. boots(16w) 8000h~800fh buffer0 bufs 0(16w) 8010h~801fh bufs 1(16w) 8020h~802fh buffer1 reserved spare 8030h~8fffh n/a reg. reserved reg. 9000h~efffh register(4kw) f000h~ffffh reg. not support not support not support figure 12. the boundary of synchronous read * reserved area is not available on synchronous read
onenand128 flash memory 43 programmable burst read latency the programmable burst read latency feature indicates to the devic e the number of additional clock cy cles that must elapse afte r avd is driven active before data will be available. upon power up, th e number of total initial access cycles defaults to four cloc ks. the number of total initial access cycles is programmable from three to seven cycles. 4-, 8-,16-, 32- word linear burst read as well as the continuous linear burst mode, there are four(4 & 8 & 16 & 32 word) (note1) linear wrap-around mode, in which a f ixed number of words are read from consecutive addresses. when the last word in the burst mode is reached, assert /ce and /oe high t o terminate the operation. in these modes, the start addres s for burst read can be any address of address map. (note 1) 32 word linear burst read isn?t available on spare area bufferram figure 13. example of 4 clock burst read latency handshaking the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initia l cycle for optimal burst mode, the host should use the programma ble burst read latency configuration.(see "system configuration1 regi ster" for details.) the rising edge of rdy which is derived fr om 1 clock ahead of data fetch clock indicates the initial word of valid burst data. output disable mode when the ce or oe input is at v ih , output from the device is disabled. th e outputs are placed in the high impedance state. table 7. burst address sequences start addr. burst address sequence(decimal) continuous burst 4-word burst 8-word burst 16-word burst 32-word burst wrap around 0 0-1-2-3-4-5-6... 0-1-2-3-0... 0-1-2-3-4-5-6-7-0... 0-1-2-3-4-....-13-14-15-0... 0-1-2-3-4-....-29-30-31-0... 1 1-2-3-4-5-6-7... 1-2-3-0-1... 1-2-3-4-5-6-7-0-1... 1-2-3-4-5-....-14-15-0-1... 1-2-3-4-5-....-30-31-0-1... 2 2-3-4-5-6-7-8... 2-3-0-1-2... 2-3-4-5-6-7-0-1-2... 2-3-4-5-6-....-15-0-1-2... 2-3-4-5-6-....-31-0-1-2... . . . . . . . . . . . . t iaa hi-z ce clk avd oe rdy t rdys t rdya dq0: dq15 d6 d7 d0 d1 d2 d3 d7 d0 hi-z 01234 t ba rising edge of the clock cycle following last read latency triggers next burst data a0: a15 valid address -1 56
onenand128 flash memory 44 program operation the device can be programmed in data unit. programming is writing 0's into the memory array by executing the internal program r ou- tine. in order to perform the internal program routine, comm and sequence is necessary. first, host sets the address of the buff er- ram and the memory location and loads the data to be programmed into the bufferram. second, program command initiates the internal program routine. during the execution of the routine, th e host is not required to provi de further controls or timings. during the internal program routine, commands except reset command written to the device will be ignored. note that a reset during a progr am operation will cause data corruption at the corresponding location. the device provides dual data buffer memory architecture. the device is capable of data -write operation from host to one of dat a buff- ers during program operation from anther data buffer to flash simu ltaneously. refer to the information for more details in "rea d while load operation". figure 14. program operation flow-chart : if program operation re sults in an error, map out the block including the page in error and copy the target data to another block. * note 1) data input could be done anywhere between "start" and "write program command". start write 0 to interrupt register data input yes add: f241h dq=0000h write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write data into dataram 1) add: dp dq=data-in program completed write ?program? command add: f220h dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? program error yes no no
onenand128 flash memory 45 within a block, the pages must be programme d consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. r andom page address programming is prohibited. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 addressing for pr ogram operation : : : :
onenand128 flash memory 46 copy-back program operation the copy-back program is confi gured to quickly and efficiently rewrite data stored in one page by sector unit(1/2 sector) witho ut utiliz- ing an external memory. since the time-cons uming cycles of serial access and re-loading cycles are removed, the system perfor- mance is improved. the benefit is especiall y obvious when a portion of a block is updated and the rest of the block also need t o be copied to the newly assigned free block. the operation for performi ng a copy-back program is a sequential execution of page-rea d without serial access and copying-program with the address of destination page. figure 15. copy back program operation flow-chart note 1) selected dataram by bsa & bsc is used for copy back operation, so previous data is overwritten. : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * start write 0 to interrupt register add: f241h dq=0000h write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?fcba? of flash add: f102h dq=fcba write ?fcpa, fcsa? of flash add: f103h dq=fcpa, fcsa copy back completed write ?copy-back program? command add: f220h dq=001bh wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc 1)
onenand128 flash memory 47 copy-back program operation with random data input the copy-back program operation with random data input in o nenand consists of 2 phase, load data into dataram, modify data and program into designated page. data from the source page is saved in one of the on-chip dataram buffers and modified by the host, then programmed into the destination page. as shown in the flow chart, data modificati on is possible upon completion of load operat ion. ecc is also available at the end o f load operation. therefore, using hardware ecc of onen and, accumulation of 1 bit error can be avoided. copy-back program operation with random data input will be effe ctively utilized at modifying ce rtain bit, byte, word, or sector of source page to destination p age while it is being copied. start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes status register map out write 0 to interrupt register add: f241h dq=0000h copy back completed wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no random data input write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?program? command add: f220h dq=0080h or 001ah write 0 to interrupt register add: f241h dq=0000h add: random address in selected dataram dq=data figure 16. copy-back program operation with random data input flow chart
onenand128 flash memory 48 erase operation the device can be erased in block unit. to erase a block is to write 1 s into the desired memory block by executing the internal erase routine. in order to perform the internal erase routine, co mmand sequence is necessary . first, host sets the block address of t he memory location. second, erase command initiates the internal eras e routine. during the execution of the routine, the host is n ot required to provide further controls or timings. during the internal erase routine, commands except reset and erase suspend command written to the device will be ignored. note that a reset during a erase operation will cause data corruption at the corresponding location. figure 17. erase operation flow-chart start write ?fba? of flash add: f100h dq=fba write ?erase? command add: f220h dq=0094h wait for int register add: f241h dq=[15]=int add: f240h dq[10]=error erase completed dq[10]=0? yes erase error no low to high transition read controller status register write 0 to interrupt register add: f241h dq=0000h
onenand128 flash memory 49 multi block erase and multi block erase verify read operation the device can be simultaneously erased in mu lti blocks unit, too. the bl ock address of the memory location and multi block era se command may be repeated for erasing multi blocks. the final bloc k address and block erase command initiate the internal multi block erase routine. during multi block eras e routine, if the command except multi bl ock erase command is written before block erase command is issued, multi block eras e operation will be aborted. erase sus pend command is allowed only when int is low after block erase command is issued. pass/fail status of each block in multi block erase operation can be read by writin g each block address and multi block erase v erify read command. but the information of the failed address has to be managed by the firmware. after block erase operation, the pas s/ fail status can be read with multi block erase verify read command, too. note that a reset during a erase operation will cause data corruption at the corresponding location. figure 18. multi block erase operation flow-chart note: 1. if there are the locked blo cks in the specified ra nge, the oper ation works as the follows. case 1. [ba(1)+0095h] + [ba(2, locked)+0095h] + ... + [ba(n-1)+0095h] + [ba(n)+0094h] = all specified blocks except ba(2) ar e erased. case 2. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ba(n, locked)+0094h] = if the last command, block erase co mmand, is put together with the locked block address, multi block erase o peration doesn?t start and is suspended until right command and addr ess input. case 3. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ba(n, locked)+0094h] + [ba(n+1)+0094h]= all specified block s except ba(n) are erased. 2. the ongo bit of controller status register is set to ?1?(bu sy) from the time of writing the 1st block address to be latched until the actual erase has fin- ished. 3. even though the failed blocked happen during multi block eras e operation, the device continues the erase operation until oth er specified blocks are erased. start write ?fba? of flash add: f100h dq=fba write ?multi block erase? add: f220h dq=0095h wait for int register add: f241h dq=[15]=int final multi block yes no low to high transition write 0 to interrupt register add: f241h dq=0000h command erase? write ?fba? of flash add: f100h dq=fba write ?block erase add: f220h dq=0094h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h command? multi block erase verify read write ?fba? of flash add: f100h dq=fba write ?multi block erase add: f220h dq=0071h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h verify read command? read controller add: f240h dq[10]=error status register dq[10]=0? multi block erase completed final multi block yes no erase address? erase completed yes erase error no
onenand128 flash memory 50 erase suspend / resume erase suspend command interrupts block erase and multi block erase to load or program data in a block that is not being erased. when erase suspend command is written during block erase and mu lti block erase operation, t he device requires a maximum of 500us to suspend erase operation. after the erase operation has been suspended, the device is available for loading or programm ing data in a block that is not being erased. for the erase susp end period, block erase, multi block erase and erase suspend com- mands are not accepted. when erase resume command is executed, bl ock erase and multi block erase operation wi ll resume. the erase resume operation does not actually resume the erase, but starts it again from the beginning. when erase suspend and erase resume command is executed, the addresses are in don?t care state. figure 19. erase suspend and resume operation flow-chart 2) if otp access mode exit happens with reset operation during erase suspend mode, reset operation could hurt the erase operation. so if a user wants to exit from otp access mode without the erase operation stop, reset nand flash core command should be used. start write ?erase suspend add: f220h dq=00b0h wait for int register add: f241h dq=[15]=int low to high transition for 500us command? 1) write 0 to interrupt register add: f241h dq=0000h write ?erase resume add: f220h dq=0030h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h command? another operation * * another operation ; load, program copy-back program, otp access 2) , hot reset, flash reset, cmd reset, multi block erase verify, lock, lock-tight, unlock check controller status register do multi block erase verify read in case of block erase in case of multi block erase note 1) erase suspend command input is prohibited during multi block erase address latch period.
onenand128 flash memory 51 otp operation the device supports one block sized otp area, which can be re ad, programmed and locked with the same sequence as normal operation. but this otp block could not be er ased. this block is separated from nand fl ash array, so it could be accessed by ot p access command instead of fba. if user wants to exit from otp access mode, cold, warm and hot reset operation should be done. but if otp access mode exit happens with reset operation during erase suspend mode, reset operation could hurt the erase oper- ation. so if user wants to exit from otp access mode with out the erase operation stop, ?reset nand flash core? command should be used. otp area is one block size(64kb, 64pages) and is divided by two areas. the first area from page 0 to page 19, total 20pages, is assigned for user and the second area from page 20 to page 63, total 44pages, are occupied for the device manufacturer. the sec - ond area is programmed prior to shipping, so this area could not be used by user. this block is fully guaranteed to be a valid block. otp block page allocation information area page use user 0 ~ 19 (20 pages) designated as user area manufacturer 20 ~ 63 (44 pages) use d by the device manufacturer page:1kb+32b sector(main area):512b sector(spare area):16b figure 20. otp area structure and assignment one block: 64kb+2kb 64pages manufacturer area : page 20 to page 63 20pages user area : page 0 to page 19 20pages
onenand128 flash memory 52 figure 21. otp load operation flow-chart otp load(otp access+load nand) otp area is separated from nand flash array, so it is acce ssed by otp access command instead of fba. the content of otp could be loaded with the same sequence as norm al load operation after being accessed by the command. if user wants to exit from otp access mode, cold, warm, hot, and nand flash core reset operation should be done. start wait for int register add: f241h dq[15]=int write 0 to interrupt register add: f241h dq=0000h write 0 to interrupt register add: f241h dq=0000h write ?fpa, fsa? of flash 1) add: f107h dq=fpa, fsa otp load completed write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int write ?otp access? command add: f220h dq=0065h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc low to high transition do cold/warm/hot otp exit host reads data from dataram note 1) fba(nand flash block address) could be omitted or any address. /nand flash core reset write ?fba? of flash 1) add: f100h dq=fba
onenand128 flash memory 53 figure 22. otp program operation flow-chart otp programming(otp access+program nand) otp area could be programmed with the same sequence as norma l program operation after being accessed by the command. to avoid the accidental write, fba should point the unlocked area address among nand flash array address map even though otp area is separated from nand flash array. start data input write ?otp access? command add: f220h dq=0065h write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write data into dataram 2) add: dp dq=data-in otp programming completed write program command dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int no add: f220h wait for int register add: f241h dq[15]=int write 0 to interrupt register add: f241h dq=0000h low to high transition otp exit automatically checked update controller add: f240h status register wait for int register low to high transition add: f241h dq[15]=int otp exit automatically otp l =0? yes no updated read controller status register add: f240h dq[10]=1(error) dq[14]=1(lock), dq[10]=1(error) add: f200h dq=bsa, bsc note 1) fba(nand flash block address) could be omitted or any address. write ?fba? of flash add: f100h dq=fba 3) 3) fba should point the unlocked area address among nand flash array address map. write 0 to interrupt register add: f241h dq=0000h read controller status register add: f240h dq[10]=0(pass) do cold/warm/hot /nand flash core reset do cold/warm/hot /nand flash core reset write ?fba? of flash 1) add: f100h dq=fba 2) data input could be done anywhere between "start" and "write program command".
onenand128 flash memory 54 otp lock(otp access+lock otp) otp area could be locked by programming xxxch to 8th word in sect or0 of page0 to prevent the program operation. at the device power-up, the device automatically checks this word and updates otp l bit of controller status register as "1"(lock). if the program operation happens in otp locked status, the device updates e rror bit of controller status register as "1"(fail). start write ?fpa, fsa? of flash add: f107h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=0001h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register add: f241h dq=0000h automatically updated dq=xxxch in spare0/sector0/page0 figure 23. otp lock operation flow-chart update controller add: f240h status register otp lock completed dq[6]=1(otp l ) write ?fba? of flash add: f100h dq=fba 3) write ?otp access? command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h do cold reset write ?fba? of flash 1) add: f100h dq=fba note 1) fba(nand flash block address) could be omitted or any address. 3) fba should point the unlocked area address among nadnd flash array address map. 2) data input could be done anywhere between "start" and "write program command".
onenand128 flash memory 55 read while load page a page b 1) load 2) load data buffer1 data buffer0 2) read the device provides dual data buffer memo ry architecture. the device is capable of data-read operation from one data buffer and data-load operation to another data buffer simultaneously. this is so called the read wh ile load operation with dual data buffer arch itecture, this feature provides the c apability of executing reading data from one of data buffers during data-load operation from flash to the other buffer simultaneously. refer to the information for more details in "load operation" before performing read while load operation. simultaneous load and read operat ion to same data buffer is prohibited. int_reg : interrupt register address add_reg : address register address flash_add : flash address to be loaded dbn_add : dataram address to be loaded cmd_reg : command register address ld_cmd : load command data load_dbn : load data from nand flash array to dataramn cs_reg : controller status register address data read_dbn : read data from dbn dbn_radd : dataram address to be read page b add we oe int 0~15 2) 2) page a 1) add_ reg int_ reg cmd_ reg cs_ reg data load _db0 data load _db1 data read _db0 * add_ reg int_ reg cmd_ reg add_ reg add_ reg db1 _add ld_ cmd read status db0 _add 0000h ld_ cmd flash dq 0~15 1) data load _db0 db0_radd* data load _db1 _add 0000h flash _add
onenand128 flash memory 56 the device provides dual data buffer memory architecture. the device is capable of data-write operation and program operation simultaneously. this is so called the write while program operation with dual data buffer architecture, this feature provides the capability of executing data-write operat ion from host to one of data buffers during pro- gram operation from anther data buffer to flash simultaneously. re fer to the information for more details in "program operation " before performing write while program oper- ation. simultaneous program and write operation to same data buffer is prohibited. page a page b 2) program 3) program data buffer1 data buffer0 1) write 2) write write while program 3) write add_reg : address register address dbn_add : dataram address to be programmed dbn_wadd : dataram address to be written data write_dbn : write data to dataramn flash_add : flash address to be programmed int_reg : interrupt register address cmd_reg : command register address pd_cmd : program command data pgm_pagea : program data from dataram to pagea cs_reg : controller status register address page b add oe int 0~15 page a 1) we db0_wadd* add_ reg add_ reg int_ reg cmd_ reg cs_ reg int_ reg cmd_ reg data pgm _pageb dq 0~15 db0 _add flash _add 0000h pd_ cmd data write _db1 * db1 _add read status 0000h pd_ cmd data pgm _pagea data write _db0 * db1_wadd* data pgm _pagea 2) add_ reg add_ reg flash _add data write _db0 * db0_wadd* data pgm _pageb
onenand128 flash memory 57 ecc operation while the device transfers data from buffer ram to nand flash array page buffer for program operation, the device hiddenly gener - ates ecc(24bits for main area data and 10bits for 2nd and 3rd word data of each sector spare area) and while load operation, hid- denly generates ecc and detects error number and position and correc ts 1bit error. ecc is updated by the device automatically. after load operation, host can know whether there is error or not by reading ?ecc status register ?(refer to ecc status register table). in addition, onenand supports 2bit edc even though it is li ttle probable that 2bit error occurs. hence, it is not recom meded that host reads ?ecc status register? for checking ecc error bec ause the built-in error correction logic of onenand finds out a nd corrects ecc error. when the device loads nand flash array main and sprea area data with ecc operation, the device does not place the newly gener- ated ecc for main and spare area into the buffer but places ecc which was generated and written in program operation into the buffer. ecc operation is done during the boot loading operation. ecc bypass operation ecc bypass operation is set by 9th bit of system configuration 1 register. in ecc bypass operation, the device neither generate s ecc result which indicates error position nor updates ecc code to nand flash arrary spare area in program operation(refer to ec c result register tables). during load operation, the on-chip ecc engine does not generate a new ecc internally and the values of ecc status and result registers are invalid. hence, in ecc bypass operation, the error cannot be detected and corrected by onenand itself. ecc bypass operation is not recommended to host. table 8. ecc code & result status by ecc operation mode note: 1. pre-written ecc code : ecc code whic h is previously written to nand flash spare area in program operation. operation program operation load operation ecc code update to nand flash array spare area ecc code at bufferram spare area ecc status & result update to registers 1bit error ecc operation update pre-written ecc code (1) loaded update correct ecc bypass not update pre-written code loaded invalid not correct
onenand128 flash memory 58 data protection during power down the device is designed to offer protection fr om any involuntary program/erase during pow er-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.3v. rp pin provides hardware protection and is recommended to be kept at v il before power-down. figure 24. data protection during power down v cc rp nand write protected idle one nand reset int onenand operation typ. 1.3v 0v
onenand128 flash memory 59 technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose re liability is not guaranteed by samsung. the infor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the sam e quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the per for- mance of valid block(s) because it is isolated from the bit line and the common s ource line by a select transistor. the system design must be able to mask out the invalid block( s) via address mapping. the 1st block, wh ich is placed on 00h block address, is full y guar- anteed to be a valid block. all device locations are erased(ffff h) except locations where the invalid block(s) information is written prior to shipping. th e invalid block(s) status is defined by the 1st word in the spare area. samsung makes sure that either the 1st or 2nd page of every inval id block has non-ffffh data at the 1st word of sector0. since the invalid block information is also erasable in most cases, it i s impos- sible to recover the information once it has been erased. therefor e, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid bl ock table via the following sugg ested flow chart(figure 24). any intentional erasure of the original in valid block information is prohibited. figure 25. flow chart to create invalid block table. start set block address = 0 check " increment block address last block ? end no yes yes create (or update) no invalid block(s) table ffffh" ? * check "ffffh" at the sector0 1st word of the 1st and 2nd page in the block
onenand128 flash memory 60 error in write or load operation within its life time, additional invalid bl ocks may develop with the device. refer to the qualification report for the actual d ata.the fol- lowing possible failure modes should be cons idered to implement a highly reliable system . in the case of status read failure af ter erase or program, block replacement should be done. because pr ogram status fail during a page program does not affect the data of the other pages in the same block, block replacement can be ex ecuted with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement load single bit failure error co rrection by ecc mode of the device block replacement when an error happens in the nth page of the block ?a? during program operation. * step1 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b? via data buffer0. * step2 copy the nth page data of the block ?a? in the data buffer1 to the nth page of another free block. (block ?b?) do not further erase or program block ?a? by creati ng an ?invalid block? tabl e or other appropriate scheme. data buffer1 of the device 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 data buffer0 of the device 1 (assuming maintain the nth page data) technical notes (continued)
onenand128 flash memory 61 one of the best features onenand has is t hat it can be a booting device itself since it contains an internally built-in boot lo ader despite the fact that its core architecture is based on nand flash. thus, onenand does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system. as the system power is turned on, the boot code originally stored in nand flash arrary is moved to bootram automatically and th en fetched by cpu through the same interface as sram?s or nor flash? s if the size of the boot code is less than 1kb. if its size i s larger than 1kb and less than or equal to 2kb, only 1kb of it can be mo ved to bootram automatically and fetched by cpu, and the rest o f it can be loaded into one of the datarams w hose size is 1kb by load command and cpu can take it from the dataram after finish- ing the code-fetching job for bootram. if it s size is larger than 2kb, the 1kb portion of it can be moved to bootram automatica lly and fetched by cpu, and its remaining part can be moved to dram through two datarams using dual buffering and taken by cpu to reduce cpu fetch time. a typical boot scheme usually used to boot the system with onenand is explained at figure 26 and figure 27. in this boot scheme , boot code is comprised of bl1, where bl stands for boot loader, b l2, and bl3. moreover, the size of the boot code is larger tha n 2kb (the 3rd case above). bl1 is called primary boot loader in other words. here is the table of detailed explanations about th e func- tion of each boot loader in this specific boot scheme. boot loaders in onenand nand flash array of onenand is divided into the partitions as described at figure 26 to show where each component of code is located and how much portion of the overall nand flash arra y each one occupies. in addition, the boot sequence is listed below and depicted at figure 27. boot sequence : 1. power is on bl1 is loaded into bootram 2. bl1 is executed in bootram bl2 is loaded into dram through two datarams using dual buffering by bl1 3. bl2 is executed in dram os image is loaded in to dram through two datarams using dual buffering by bl2 4. os is running boot loader description bl1 moves bl2 from nand flash array to dra m through two datarams using dual buffering bl2 moves os image (or bl3 opt ionally) from nand flash array to dram through two datarams using dual buffering bl3 (optional) moves or writes the image through usb interface technical notes (continued) boot sequence
onenand128 flash memory 62 figure 26. partition of nand flash array reservoir file system os image bl2 bl1 os image bl 2 nand flash array onenand dram figure 27. onenand boot sequence 2 3 1 internal bufferram data ram 1 data ram 0 boot ram(bl 1) note : and can be copied into dram through two datarams using dual buffering 2 3 technical notes (continued) reservoir file system os image nbl3 nbl2 nbl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 page 63 page 62 page 2 page 1 page 0 bl2 partition 4 partition 3 reservoir file system os image bl3 bl2 bl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 partition 4 partition 3 : : bl1 block 512
onenand128 flash memory 63 there are two methods of determining interrupt status on the onen and. using the int pin or monitoring the interrupt status regi s- ter bit. the onenand int pin is an output pin function used to notify the host when a command has been completed. this provides a hard- ware method of signaling the completion of a program, erase, or load operation. in its normal state, the int pin is high if the int polarity bi t is default. before a command is written to the command registe r, the int bit must be written to '0' so the int pin transitions to a lo w state indicating start of the operation. upon completion of the command operation by the onenand?s internal controller, int returns to a high state. int is an open drain output allowing multiple int outputs to be or -tied together. int does not float to a hi-z condition when t he chip is deselected or when outputs are disabled. refer to section 2.8 for additional information about int. int can be implemented by tying int to a host gpio or by continuous polling of the interrupt status register. int can be tied to a host gpio to detect the rising edge of int, signaling the end of a command operation. this can be configured to operate either synchronously or asynchronously as s hown in the diagrams below. int command technical notes (continued) methods of determining interrupt status the int pin to a host general purpose i/o
onenand128 flash memory 64 synchronous mode using the int pin when operating synchronously, int is tied directly to a host gpio. an alternate method of determining the end of an operation is to continuously monitor the interrupt status register bit instead of using the int pin. host onenand asynchronous mode using the int pin when configured to operate in an asynchronous mode, /ce and /avd of the onenand are tied to /ce of the host. clk is tied to the host vss (ground). /rdy is tied to a no-connect. /oe of the o nenand and host are tied together and int is tied to a gpio. rdy oe clk ce rdy oe clk ce avd avd gpio int host onenand n.c oe vss ce rdy oe clk ce avd gpio int int command this can be configured in either a sync hronous mode or an asynchronous mode. polling the interrupt register status bit technical notes (continued)
onenand128 flash memory 65 synchronous mode using interrupt status register bit polling when operating synchronously, /ce, /avd, clk, /rdy, /oe, and dq pins on the host and onenand are tied together. host onenand rdy oe clk ce rdy oe clk ce avd avd dq dq asynchronous mode using interrupt status register bit polling when configured to operate in an asynchronous mode, /ce and /avd of the onenand are tied to /ce of the host. clk is tied to the host vss (ground). /rdy is tied to a no-connect. /o e and dq of the onenand and host are tied together. host onenand n.c oe ce rdy oe clk ce avd dq dq vss technical notes (continued)
onenand128 flash memory 66 tr,tf ibusy [ma] rp(ohm) ibusy tr[us] @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 10k 20k 30k 0.089 tf[ns] 0.7727 1.345 1.788 3.77 3.77 3.77 3.77 1.75 0.18 0.09 40k 50k 2.142 2.431 3.77 3.77 0.045 0.06 0.036 open(100k) 5.420 0.000 busy state ready vcc voh tf tr vol vss ~50k ohm int internal vcc rp int pol = ?high? determing rp value because the pull-up resistor value is related to tr(int), an appr opriate value can be obtained by the following reference chart s. technical notes (continued)
onenand128 flash memory 67 ~50k ohm int internal vcc rp int pol = ?low? tr,tf ibusy [ma] rp(ohm) ibusy tf[us] @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 10k 20k 30k 0.067 tr[ns] 0.586 1.02 1.356 6.49 6.49 6.49 6.49 1.75 0.18 0.09 40k 50k 1.623 1.84 6.49 6.49 0.045 0.06 0.036 open(100k) 4.05 0.000 busy state ready voh tf tr vol vss vcc technical notes (continued)
onenand128 flash memory 68 absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during transitions, this level should not fall to por level(typ. 1.5v). maximum dc voltage is vcc+0.6v on input / output pins wh ich, during transitions, may overs hoot to vcc+2.0v for periods <20n s. 2. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. ex posure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit kfg2816q1m kfg2816d1m kfg2816u1m voltage on any pin relative to v ss vcc vcc -0.5 to + 2.45 -0.6 to + 4.6 -0.6 to + 4.6 v all pins v in -0.5 to + 2.45 -0.6 to + 4.6 -0.6 to + 4.6 temperature under bias extended t bias -30 to +125 -30 to +125 -30 to +125 c industrial - - -40 to +125 storage temperature t stg -65 to +150 -65 to +150 -65 to +150 c short circuit output current i os 555ma operating temperature extended t a -30 to + 85 -30 to + 85 -30 to + 85 c industrial t a - - -40 to + 85 9.2 recommended operating conditions ( voltage reference to gnd ) notes : 1. the system power should reach 1.7v after por triggering level(typ. 1.5v) within 400us. 2. vcc-core should reach the operating voltage level prior to vcc-io or at the same time. parameter symbol 1.8v device 2.65v device 3.3v device unit min typ. max min typ. max min typ. max supply voltage v cc- core 1.7 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v v cc- io v ss 000000000v
onenand128 flash memory 69 dc characteristics 1. ce should be vih for rdy. iobe should be ?0? for int. 2. icc active for host access 3. icc active while internal operation is in progress. parameter symbol test conditions 1.8v device 2.65v device 3.3v device unit min typ max min typ max min typ max input leakage current i li v in =v ss to v cc , v cc =v ccmax - 1.0 - + 1.0 - 1.0 - + 1.0 - 1.0 - + 1.0 a output leakage cur- rent i lo v out =v ss to v cc , v cc =v ccmax , ce or oe =v ih (note 1) - 1.0 - + 1.0 - 1.0 - + 1.0 - 1.0 - + 1.0 a active asynchronous read current (note 2) i cc1 ce =v il , oe =v ih - 8 15 - 10 20 - 10 20 ma active burst read cur- rent (note 2) i cc2 ce =v il , oe =v ih 54mhz - 12 20 - 20 30 - 20 30 ma 1mhz - 3 4 - 4 6 - 4 6 ma active write current (note 2) i cc3 ce =v il , oe =v ih - 8 15 - 10 20 - 10 20 ma active load current (note 3) i cc4 ce =v il , oe =v ih , we =v ih, v in =v ih or v il -2025-2030-2030ma active program cur- rent (note 3) i cc5 ce =v il , oe =v ih , we =v ih, v in =v ih or v il -2025-2030-2030ma erase/multi block erase current (note 3) i cc6 ce =v il , oe =v ih , we =v ih , v in =v ih or v il, 64blocks -1520-1825-1825ma standby current i sb ce = rp =v cc 0.2v - 10 50 - 15 50 - 15 50 a input low voltage v il - -0.5 - 0.4 -0.5 - 0.4 0 - 0.8 v input high voltage v ih - v ccq - 0.4 - v ccq +0.4 v ccq - 0.4 - v ccq +0.4 0.7*v ccq -v ccq v output low voltage v ol i ol = 100 a , v cc =v ccmin , v ccq =v ccqmin --0.2--0.2-- 0.22* vccq v output high voltage v oh i oh = -100 a , v cc =v ccmin , v ccq =v ccqmin v ccq - 0.1 -- v ccq - 0.4 -- 0.8*v ccq --v
onenand128 flash memory 70 valid block notes: 1. the device may include invalid blo cks when first shipped. additional invalid blocks may develop while being used. the number of valid blo cks is pre- sented with both cases of invalid blocks considered. invalid bloc ks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. 2. the 1st block, which is placed on 00h block ad dress, is fully guaranteed to be a valid block. parameter symbol min typ. max unit valid block number n vb 251 - 256 blocks ac test condition (v cc = 1.8v/2.65v/3.3v) parameter value input pulse levels 0v to v cc input rise and fall times clk 3ns other inputs 5ns input and output timing levels vcc/2 output load c l = 30pf 0v v cc v cc /2 v cc /2 input pulse and test point input & output test point capacitance (t a = 25 c, v cc = 1.8v/2.65v/3.3v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in1 v in =0v - 10 pf control pin capacitance c in2 v in =0v -10pf output capacitance c out v out =0v - 10 pf output load device under te s t * c l = 30pf including scope and jig capacitance
onenand128 flash memory 71 synchronous burst read note 1. if oe is disabled at the same time or before ce is disabled, the output will go to high-z by t oez (max. 17ns). if ce is disabled at the same time or before oe is disabled, the output will go to high-z by t cez (max. 20ns). if ce and oe are disabled at the same time, th e output will go to high-z by t oez (max. 17ns). these parameters are not 100% tested. 2. it is the following clock of address fetch clock. parameter symbol kfg2816x1m unit min max clock clk 1 54 mhz clock cycle t clk 18.5 - ns initial access time(at 54mhz) t iaa -76ns burst access time valid clock to output delay t ba - 14.5 ns avd setup time to clk t avds 7-ns avd hold time from clk t avdh 7-ns address setup time to clk t acs 7-ns address hold time from clk t ach 7-ns data hold time from next clock cycle t bdh 4-ns output enable to data t oe -20ns ce disable to output high z t cez 1) -20ns oe disable to output high z t oez 1) -17ns ce setup time to clk t ces 7-ns clk high or low time t clkh/l t clk /3 - ns clk 2) to rdy valid t rdyo - 14.5 ns clk to rdy setup time t rdya - 14.5 ns rdy setup time to clk t rdys 4-ns ce low to rdy valid t cer -15ns
onenand128 flash memory 72 switching waveforms note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. 5 cycles for initial access shown. t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk ce clk avd oe dq0-dq15 a0-a15 d6 d7 d0 d1 d2 d3 d7 t rdya figure 29. continuous linear burst mode with wrap around t oe brl=4 figure 28. 8 word linear burst mode with wrap around t cez t oez d0 t clkh t clkl t rdyo t cer 5 cycles for initial access shown. t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk hi-z ce clk avd oe dq0-dq15 rdy a0-a15 t rdys da da+1 da+2 da+3 da+4 da+5 da+n t rdya t oe brl=4 t cez t oez da+n+1 hi-z t rdyo t cer hi-z rdy t rdys hi-z
onenand128 flash memory 73 asynchronous read note: 1. if oe is disabled at the same time or before ce is disabled, the output will go to high-z by t oez (max. 17ns). if ce is disabled at the same time or before oe is disabled, the output will go to high-z by t cez (max. 20ns). if ce and oe are disabled at the same time, the output will go to high-z by t oez (max. 17ns). these parameters are not 100% tested. parameter symbol kfg2816x1m unit min max access time from ce low t ce -76ns asynchronous access time from avd low t aa -76ns asynchronous access time from address valid t acc -76ns read cycle time t rc 76 - ns avd low time t avdp 12 - ns address setup to rising edge of avd t aavds 7-ns address hold from rising edge of avd t aavdh 7-ns output enable to output valid t oe -20ns ce setup to avd falling edge t ca 0-ns ce disable to output & rdy high z 1) t cez -20ns oe disable to output & rdy high z 1) t oez -17ns switching waveforms figure 30. asynchronous read mode(avd toggling) note: va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 clk v il avd hi-z hi-z rdy t avdp t aavdh dq0-dq15 t cez case 1 : valid address and avd transition occur before ce is driven to low
onenand128 flash memory 74 figure 31. asynchronous read mode(avd toggling) note: va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 clk v il avd t aa hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez case 2 : avd transition occurs after ce is driven to low and valid address transition occurs before avd is driven to low case 3 : avd transition occur after ce is driven to low and valid address transition occurs after avd is driven to low figure 32. asynchronous read mode(avd toggling) note: va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 t acc clk v il avd t aavds hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez
onenand128 flash memory 75 figure 33. asynchronous read mode(avd tied to ce ) note: va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 t acc clk v il hi-z hi-z rdy t rc dq0-dq15 t cez case 4 : avd is tied to ce
onenand128 flash memory 76 ac characteristics asynchronous write operation parameter symbol kfg2816x1m unit min typ max we cycle time t wc 70 - - ns avd low pulse width t avdp 12 - - ns address setup to rising edge of avd t aavds 7--ns address setup to falling edge of we t awes 0 address hold to rising edge of avd t aavdh 7--ns address hold to rising edge of we t ah 10 ns data setup to rising edge of we t ds 10 - - ns data hold from rising edge of we t dh 4--ns ce setup to falling edge of we t cs 0--ns ce hold from rising edge of we avd toggled t ch1 0--ns ce hold from rising edge of we avd tied to ce t ch2 10 - - ns we pulse width t wpl 40 - - ns we pulse width high t wph 30 - - ns avd disable to we disable t vlwh 15 - - ns we disable to avd enable t wea 15 - - ns
onenand128 flash memory 77 figure 34. latched asynchronous write mode(avd toggling) ce we oe t cs valid wd t ds va valid wd t wpl t wph t wc t aavds t dh avd t aavdh va rdy hi-z hi-z a0-a15 dq0-dq15 t wea clk v il case 1 : avd is toggled every write cycle note: va=valid read address, wd=write data. t avdp t vlwh t ch1 t ch1 t cs
onenand128 flash memory 78 figure 35. asynchronous write mode(avd toggling) case 2 : avd is synchronized with ce note: va=valid read address, wd=write data. avd ce we oe t cs valid wd t ds valid wd t wpl t wph t wc t dh va rdy hi-z hi-z a0-a15 dq0-dq15 clk v il t ch2 t awes t ah va t ch2 t cs
onenand128 flash memory 79 figure 36. asynchronous write mode(avd tied to ce ) case 3 : avd is tied to ce note: va=valid read address, wd=write data. ce or avd we oe t cs valid wd t ds valid wd t wpl t wph t wc t dh va rdy hi-z hi-z a0-a15 dq0-dq15 clk v il t ch2 t awes t ah va t ch2 t cs
onenand128 flash memory 80 reset note: these parameters are tested based on int bit of interrupt r egister. because the time on int pin is related to the pull-up and pull-down resistor value. please refer to page 66 and 67. parameter symbol kfg2816x1m unit min max rp & reset command latch(during load routines) to int high (note) t rst -10 s rp & reset command latch(during program routines) to int high (note) t rst -20 s rp & reset command latch(during erase routines) to int high (note) t rst - 500 s rp & reset command latch(not during internal routines) to read mode (note) t rst -10 s int high to read mode (note) t ready 200 - ns rp pulse width t rp 200 - ns figure 37. reset timing switching waveforms ce , oe rp t rp t ready t rst int bit avd bp or f220h int bit ai we ce hot reset t rst dqi 00f0h or 00f3h warm reset oe t ready
onenand128 flash memory 81 performance notes: 1. these parameters are tested based on int bit of interrupt regi ster. because the time on int pin is related to the pull-up an d pull- down resistor value. please refer to page 66 and 67. parameter symbol min typ max unit sector load time(note 1) t rd1 -3545 s page load time(note 1) t rd2 -5075 s sector program time(note 1) t pgm1 - 320 720 s page program time(note 1) t pgm2 - 350 750 s otp access time(note 1) t otp - 600 1000 ns lock/unlock/lock-tight time(note 1) t lock - 600 1000 ns erase suspend time(note 1) t esp - 400 500 s erase resume time(note 1) 1 block t ers1 -23ms 2~64 blocks t ers2 45ms number of partial program cycles in the sector (including main and spare area) nop - - 2 cycles block erase time (note 1) 1 block t bers1 -23ms 2~64 blocks t bers2 -45ms multi block erase verify read time(note 1) t rd3 - 115 135 s
onenand128 flash memory 82 notes: 1. aa = address of address register ca = address of command register lcd = load command lma = address of memory to be loaded ba = address of bufferram to load the data bd = program data sa = address of status register 2. ?in progress? and ?complete? refer to status register 3. status reads in this figure is asynchronous read , but status read in synchronous mode is also supported. read command sequence a0:a15 we ce clk t ds t dh t ch1 t wpl t cs t wph t wc ca sa ba rcd rma aa dq0-dq15 oe read data figure 38. load operation timing switching waveforms v il load operations complete da t aavdh t aavds avd int t avdp t rd t vlwh t wea bit
onenand128 flash memory 83 notes: 1. aa = address of address register ca = address of command register pcd = program command pma = address of memory to be programmed ba = address of bufferram to load the data bd = program data sa = address of status register 2. ?in progress? and ?complete? refer to status register 3. status reads in this figure is asynchronous read , but status read in synchronous mode is also supported. program command sequence (last two cycles) a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc sa sa in progress complete aa dq0-dq15 oe read status data figure 39. program operation timing switching waveforms v il program operations avd ba ca pcd pma bd t aavdh t aavds t pgm int t avdp t vlwh t wea
onenand128 flash memory 84 notes: 1. aa = address of address register ca = address of command register ecd = erase command ema = address of memory to be erased sa = address of status register 2. ?in progress? and ?complete? refer to status register 3. status reads in this figure is asynchronous read, but status read in synchr onous mode is also supported. erase command sequence (last two cycles) a0:a15 we ce t ds t dh t ch ca sa sa in progress complete ecd ema aa dq0-dq15 oe read status data figure 40. block erase operations switching waveforms t wpl t cs t wph t wc clk v il erase operation avd t aavdh t aavds t bers int t avdp t vlwh t wea
onenand128 flash memory 85 onenand128 package dimensions 67-fbga-7.00x9.00 units:millimeters 0.10 max 0.45 0.05 0.32 0.05 0.90 0.10 bottom view top view 0.80x7=5.60 a 0.80x9=7.20 67- ? 0.45 0.05 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) #a1 index 7.00 0.10 9.00 0.10 #a1 9.00 0.10 7.00 0.10 9.00 0.10 b d a c e f g h 1 432 5 6 0.80 2.800 3 . 6 0
onenand128 flash memory 86 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 ()
onenand128 flash memory 87 ordering information k f g 28 1 6 x 1 m - x x b samsung onenand memory device type g : single chip density 28 : 128mb operating temperature range e = extended temp. (-30 c to 85 c) i = industrial temp. (-40 c to 85 c) page architecture 1 : 1kb page version m : 1st generation product line desinator b : include bad block d : daisy sample operating voltage range q : 1.8v(1.7 v to 1.95v) d : 2.65v(2.4v to 2.9v) u : 3.3v(2.7 v to 3.6v) package d : fbga(lead free) p : tsop(lead free) organization x16 organization

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